Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally<1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such a “multiple stage” apparatus the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (or mask image transfer to wafer). Another goal is to optimize illumination and enhance the contrast of an image (reproduction of circuit design) on a wafer. By increasing the overall process window (i.e., the ability to consistently print features having a specified CD regardless of whether or not the features are isolated or densely packed relative to adjacent features), one may be able to more easily accomplish each one of the goals.
Methods for optimizing the source illumination and mask patterns so as to improve the overall printing performance have been disclosed in the prior art. For example, one known technique for optimizing mask designs is referred to as optical proximity correction or OPC. In order for any optimization process to be efficient and produce useful results, it is essential to have a good model of the imaging process that can be utilized to perform simulations of the imaging process during the optimization process.
Further, in order to achieve an accurate model, it is typically necessary to utilize large amounts of wafer pattern measurement data in the model calibration process. For example, using 1-dimensional (1-D) CD values as input data for model calibration typically requires a large number of CD measurements (in the order of thousands) in order to obtain an accurate model. However, such a process can miss important information contained in the high frequency features such as corners and line ends where the pattern fidelity can impact IC device performance on the wafer.
In order to include as complete a set of information as possible about the lithography process in question, recent calibration methods are utilizing wafer SEM pictures that contain not only line or space dimension information but also include 2-dimensional (2-D) structure information. One problem arising from the use of 2-D SEM pictures for the model calibration process is that it requires the optimization step to include performing an alignment process, with sufficient accuracy, between the SEM pictures and the resist image simulated intended mask patterns (or GDSII design patterns). In other words, the calibration includes a calculation and/or optimization step to verify that the 2-D SEM pictures are properly aligned with the target pattern in addition to the optimization of optical and resist parameters (i.e., model parameters) defining the imaging process. This need in performing the alignment process results in an unwanted increase of computation time required for the model optimization/calibration process because of increased number of parameters in this type of multi-dimension non-linear optimization.
Accordingly, it is an object of the present invention to provide a model calibration process that allows for the use of 2-D structural information (or greater), but minimizes and/or reduces the increased time required for performing the initial alignment process required when utilizing 2-D structural information in the model calibration process.